| 摘要: |
| 3D芯片中硅通孔(TSV)的位置分布会对总线长造成很大影响,所以对于TSV位置分布的优化有许多算法,逐层进行TSV分配只能做到局部优化.提出用逆向重分配的方法对已有算法结果进一步优化以达到减少总线长的目的.同时提出了一种快速重分配以提高深度优化的运行时间.实验结果表明,对比逐层TSV分配方法,此逆向重分配方法可减少3.7%的总线长;此方法亦可对其他TSV分配算法(如逐网TSV分配、拉格朗日松弛算法等)所得结果作进一步线长优化;而快速重分配可将逆向重分配的运行时间降低为原来的10%. |
| 关键词: 3D芯片 硅通孔(TSV) 逆向重分配 线长优化 |
| DOI： |
| 分类号: |
| 基金项目:国家科技重大专项“TD-LTE/FDD-LTE/TD-SCDMA/WCDMA/GSM多模型基带商用芯片研发”(2013 ZX03001007-004) |
|
| An improved layer by layer TSV assignment optimization for multi-layer 3-D ICs |
|
LI Delong1, HAO Cong2, YOSHIMURA Takesi2, YU Hui1
|
|
1.School of Electronic Information and Electrical Engineering,Shanghai Jiao Tong University;2.Graduate School of Information,Production and Systems LSI,WASEDA University
|
| Abstract: |
| Poor TSV assignment algorithm leads to a large detour of wire-length.Some of the previous works deal with TSV assignment problem using layer-by-layer methods(LBL) only gets local optimal results.In this research work,a backward layer-by-layer reassignment(BRLBL) is developed to do further optimization.This reassignment algorithm takes global information into consideration and optimizes the outcome of layer-by-layer TSV assignment methods.Also a fast layer-by-layer reassignment(FLBL) method is proposed to shorten the runtime.Experimental results show that BRLBL achieves an average reduction over 3.7% of wire-length,while the FLBL improves the execution time of BRLBL by 10 times. |
| Key words: 3-D IC Through-silicon via（TSV） wire-length optimization backward reassignment |
Editorial Board